The invention relates to integrated circuit fabrication and, more particularly, to methods and apparatus for performing variable rotational assignment of interconnect levels for use in the fabrication of integrated circuits.
It is known that conventional integrated circuit (IC) fabrication processes utilize a so-called xe2x80x9cManhattan geometryxe2x80x9d to form the circuits and interconnects associated with an IC. In such a geometry, horizontal and vertical wires formed at 90xc2x0 (degrees) to one another are used to connect points across the IC or chip, while a 45xc2x0 wire is typically used in corners of the chip and, in some cases, in the internal section or interconnect, so that distances can be reduced. However, in order to implement these wires or edges in a Manhattan IC, one must adhere to the so-called xe2x80x9clitho step.xe2x80x9d The litho step is defined as the resolution movement allowed in the x or y direction. For example, in 0.35 xcexcm (micrometers), 0.25 xcexcm and 0.18 xcexcm wire sizes, the resolution step is 0.02 xcexcm. Thus, to make a horizontal wire as shown in FIG. 1, a number of these litho steps are combined to form the horizontal wire. It is to be understood that W and L are multiples of the litho step. As shown in FIG. 1, a litho step includes the horizontal, or x, movement denoted by the arrow labeled A and the vertical, or y, movement denoted by the arrow labeled B.
However, when a 45xc2x0 wire or edge is made using conventional Manhattan geometry techniques, the litho step causes the edges to become wavy, as illustrated in FIG. 2. This causes several problems. First, the database used to store the data associated with the fabrication of an IC that includes these edges increases significantly as compared to a database associated with the fabrication of only horizontal and vertical wires. The straight edges can be combined to reduce memory storage, but for 45xc2x0 edges, the step of 0.02 xcexcm in wires where W=0.3 xcexcm and L=10,000 xcexcm can be severe. Second, the extraction of this wire causes problems since the W and L are not well-defined, as illustrated by the waviness of the lines in FIG. 2. When this wire is a poly silicon gate, the extraction in a transistor causes most Computer Aided Design or CAD tools to give fictitious results, as well as increase the database size associated with the extraction. Third, the write time associated with 45xc2x0 angles or lines is longer because of the grain size or xe2x80x9clitho sizexe2x80x9d effect.
Thus, it would be advantageous to have a technique for forming a 45xc2x0 edge that allows wires to crisscross the chip, i.e., to traverse the entire chip surface rather than just the corners as in the conventional Manhattan geometry, and therefore save on interconnect distances while avoiding the waviness problem associated with the litho step. For example, as shown in FIG. 3, assume that two points A and B in the chip must communicate with one another. Using conventional techniques, the Manhattan method would allow a horizontal wire along x and a vertical wire along y. This would give a total interconnect distance between A and B of x+y.
By drawing a wire along the hypotenuse, the interconnect distance is {square root over (x2+y2)} which is less than x+y. In the case where x=y, the hypotenuse is {square root over (2x2)} while the distance between A and B in accordance with the conventional technique would be 2x. Thus, the distance is reduced by                     2            ⁢      x              2      ⁢      x        =      1          2      
or 0.707. This is about 30% (percent) less distance than the distance associated with traversing only the edges of the triangle.
Unfortunately, several problems have prevented this technique from being previously realized. For example, the three problems described above are impediments to the use of such a technique. Further, once a wire runs from one corner of the chip to the other, as illustrated in FIG. 3 by wire AB, all interconnects on this level are blocked by the wire. Thus, interconnects on this level must be made in smaller Manhattan lengths or in 45xc2x0 edges. But, as explained above, if this is done: (1) write time will increase enormously; (2) CAD extraction will be a problem; and (3) the data storage and file size will be large.
Accordingly, there is a need for IC fabrication techniques capable of forming a 45xc2x0 wire, or a wire at another angle other than 0xc2x0 or 90xc2x0, in an IC which overcome the problems described above such that wires so formed can crisscross the chip, and thus save on interconnect distances while avoiding the waviness problem associated with the litho step.
The present invention provides methods and apparatus for use in the fabrication of integrated circuits wherein non-horizontal and non-vertical wires or interconnect lines, i.e., non-0xc2x0 and non-90xc2x0 wires, respectively, are assigned to interconnect mask layers or levels separate from mask layers having horizontal and vertical wires assigned thereto. The assigned non-horizontal and non-vertical interconnect lines are then rotated to a horizontal and/or vertical orientation for printing the mask layers in which they are located. Assignment and rotation may take place within a CAD system. All mask layers may then be printed without the above-described litho step problem. Then, at the time of exposure of the appropriate metal layers of the integrated circuit, the masks associated with the non-horizontal and non-vertical wires are rotated so that the wires thereon are returned to their original non-horizontal and non-vertical orientation. The metal layers are then exposed. With the use of variable rotational assignment according to the invention and thus the elimination of the litho step problem, non-horizontal and non-vertical wires can traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points and saving on interconnect distances.
In one illustrative aspect of the invention, a method for use in fabricating at least a portion of an integrated circuit includes the following steps. First, one or more interconnect lines associated with the integrated circuit which are non-horizontal and non-vertical are assigned to at least one metal mask layer separate from at least another metal mask layer assigned to at least one of the horizontal interconnect lines and the vertical interconnect lines. Each of the one or more non-horizontal/non-vertical interconnect lines are then rotated from an original orientation by a predetermined angle determined by the original line orientation relative to the horizontal or vertical so that the one or more non-horizontal/non-vertical interconnect lines are horizontally and/or vertically oriented. It is to be appreciated that the above assigning and rotating operations may be performed by a computer system executing a CAD program.
Next, the one or more rotated non-horizontal/non-vertical interconnect lines are printed on the at least one metal mask layer assigned thereto. It is to be appreciated that the printing operation may be performed using a mask printing device such as an E-beam machine, as is known in the art.
Then, the at least one printed metal mask layer is rotated so that each of the one or more non-horizontal/non-vertical interconnect lines is returned to its original non-horizontal and non-vertical orientation. Lastly, the rotated metal mask layer is used to expose a corresponding metal layer of the integrated circuit. It is to be appreciated that the mask rotation and exposing operations may be performed in accordance with known IC fabrication equipment.
Of course, the interconnect lines which are originally intended to be horizontal and vertical and assigned to mask layers separate from the mask layers associated with the non-horizontal/non-vertical interconnect lines may be printed and used for exposure without rotation operations. Also, other non-horizontal/non-vertical features associated with the interconnect may be processed in accordance with the variable rotational assignment methodology described above. It is to be further appreciated that the scope of the present invention is also intended to encompass apparatus operative to implement the above-described methodology, as well as integrated circuits fabricated in accordance therewith.
Advantageously, the present invention eliminates various problems associated with conventional IC fabrication techniques and allows for interconnect distances to be reduced over, for example, a Manhattan interconnect by as much as 30%. Furthermore, the capacitance interaction of interconnects on lower and higher levels can be made less influential by using this invention, which from a noise coupling perspective is highly advantageous. Since the lower and upper layers are not parallel, the coupling capacitance to these interconnects will extend for only a fraction of the wire""s length. Since this wire will be crossing other wires, the capacitive interaction of these other wires can cancel the capacitance of this wire, thus allowing lower noise due to this coupling effect.
Furthermore, as the number (N) of metalization or metal layers continues to increase, the rotation assignment to each layer can be             360      ⁢      xc2x0        N    ,
or as will be explained,             180      ⁢      xc2x0        N    .
This allows for finer granularity in the placement of the interconnect.